An electrically programmable read only memory (EPROM) is a type of device having a floating gate member that is either charged or uncharged. Once charged, the electrons within the floating gate member in many EPROM devices are removed by ultraviolet light or a Fowler-Nordheim tunneling process. The tunneling erase process is usually referred to as "electrical erase". For some types of EPROM devices, the electrical erase is achieved by disconnecting the drain, grounding the control gate, and taking the source to a sufficiently positive potential, typically between 10 V and 20 V, to remove the charge from the floating gate member. An example to this kind of device is disclosed in U.S. Pat. No. 4,780,424. The process of erasing causes electrons to flow from the floating gate member to the source region through a tunnel oxide layer (a thin silicon dioxide layer) between the source region and the floating gate member. The rate at which electrons are removed from the floating gate member is determined by the potential across the tunnel oxide layer during erase. A higher potential across the tunnel oxide layer increases the rate at which electrons are removed from the floating gate producing a device with a shorter erase time.
Traditionally, the floating gate member overlaps the source region and drain region nearly symmetrically for many devices including a device disclosed in U.S. Pat. No. 4,780,424. With a symmetric floating gate member, a change in the overlap affects the charging, erasing, and reading characteristics of the device. A smaller floating gate overlap affects both the source and drain overlap on symmetrical devices. The device has less source coupling and increases the potential across the tunnel oxide during erase thereby causing the floating gate member to erase faster. The device also has less drain coupling giving a smaller floating gate potential during programming and a smaller read current, both of which are not desired. A larger floating gate overlap increases the floating gate-to-source overlap and the floating gate-to-drain overlap. A device with the larger floating gate overlap has better programming characteristics and more read current, but has a slower erase time. Therefore, the symmetric overlap does not produce optimum device performance because the floating gate overlap of the source and drain regions are not changed independently of one another.
Several types of asymmetric single cell EPROM devices are disclosed in U.S. Pat. No. 4,698,787. A single cell requires contacts to the source, drain, and control gate. When incorporated into a memory array, a significant amount of array area is occupied by contacts to the individual source, drain, and control gates. This type of cell layout decreases yield as the number of devices per substrate, and each device has a greater likelihood of failure because it occupies more substrate area.